From 25ae602d2edb9426f94fe5fee26665d498f7fd9e Mon Sep 17 00:00:00 2001 From: Kein Yuan Date: Fri, 4 Apr 2014 15:15:14 -0700 Subject: rambi: switch MCLK from 19.2Mhz to 25Mhz With following settings 1.Coreboot 25Mhz 2.Maxim codec configured with MCLK=25Mhz 2.I2C 400Khz fixed 4.Including Enable/Disable SHDN bit when LRCLK starts/Stops 5.Removed PLL toggle workaround routine. audio playing is smooth before/after S3, no noise when recording so change MCLK from 19.2 back to 25Mhz. BUG=chrome-os-partner:26948 BRANCH=firmware-rambi-5216 TEST=test audio play and record on Rambi, works fine. Change-Id: I5602feb39721344feab837ff4a3a18309a47a6a6 Signed-off-by: Kein Yuan Reviewed-on: https://chromium-review.googlesource.com/193881 Tested-by: Shawn Nematbakhsh Reviewed-by: Aaron Durbin Commit-Queue: Shawn Nematbakhsh (cherry picked from commit bfe1d535aa2f20a32e163abeb99f3d657e2b43ab) Signed-off-by: Marc Jones Reviewed-on: http://review.coreboot.org/7219 Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- src/mainboard/google/rambi/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 5587006f88..27dadca885 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -24,7 +24,7 @@ chip soc/intel/baytrail register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" # LPE audio codec settings - register "lpe_codec_clk_freq" = "19" # 19.2MHz clock + register "lpe_codec_clk_freq" = "25" # 25MHz clock register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] # SD Card controller -- cgit v1.2.3