From 1f9653a1bc737587deed507cd173595b180aad8f Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 14 Jul 2014 16:31:25 +1000 Subject: src/superio/ite/it8772f: Separate mainboard from SIO at obj level Remove #include early_serial.c and rename to early_init.c as no actual UART configuration is done here. Note that this SIO component still hard codes its base address to 0x2e. Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/6271 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/google/panther/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c index c367968f90..c90c8e7987 100644 --- a/src/mainboard/google/panther/romstage.c +++ b/src/mainboard/google/panther/romstage.c @@ -30,11 +30,11 @@ #include #include "gpio.h" #include "superio/ite/it8772f/it8772f.h" -#include "superio/ite/it8772f/early_serial.c" #include "superio/ite/common/ite.h" #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define DUMMY_DEV PNP_DEV(0x2e, 0) const struct rcba_config_instruction rcba_config[] = { @@ -145,7 +145,7 @@ void mainboard_romstage_entry(unsigned long bist) /* Early SuperIO setup */ ite_kill_watchdog(GPIO_DEV); - it8772f_ac_resume_southbridge(); + it8772f_ac_resume_southbridge(DUMMY_DEV); pch_enable_lpc(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -- cgit v1.2.3