From 1deca23f0aae91c49bb828dbea8b0a268c7c88ef Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Tue, 9 Feb 2021 12:05:29 +0800 Subject: mb/google/zork: modify ELAN TS i2c IRQ to LEVEL active for dirinboz EDGE IRQ from TS might be invalid to HOST, configure IRQs as level triggered to prevent TS lost. BUG=b:179594439 BRANCH=zork TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on, suspend DUT to check TS is functional Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416 Reviewed-by: Kangheui Won Reviewed-by: Sam McNally Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/variants/dirinboz/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 1bfea1d1c4..283b1fc0e3 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -120,7 +120,7 @@ chip soc/amd/picasso register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "enable_delay_ms" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" -- cgit v1.2.3