From 11f2f88a277124713f7b0023f078fcc2e1a98c32 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Mon, 13 Mar 2023 10:55:21 -0700 Subject: mb/google/brya: Enable asynchronous End-Of-Post Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922 Reviewed-by: Nick Vaccaro Reviewed-by: Tarun Tuli Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 2976ae2165..0080400994 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -32,6 +32,7 @@ config BOARD_GOOGLE_BRYA_COMMON select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE select SOC_INTEL_CRASHLOG -- cgit v1.2.3