From 0fec867e32a2df821e5a3569496b1dda7a2b1d5f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 25 May 2021 21:07:23 +0200 Subject: soc/amd/picasso: add devicetree setting for PSPP policy Since the default for the corresponding UPD of the Picasso FSP is DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE, add a deviectree setting for each board that's using the Picasso SoC code to not change the setting for the existing boards. Signed-off-by: Felix Held Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb | 2 ++ src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb | 2 ++ 2 files changed, 4 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index a8c270e5fe..252540093c 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -250,6 +250,8 @@ chip soc/amd/picasso register "gpp_clk_config[5]" = "GPP_CLK_OFF" register "gpp_clk_config[6]" = "GPP_CLK_OFF" + register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 840dfe7f11..89bca93d17 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -243,6 +243,8 @@ chip soc/amd/picasso register "gpp_clk_config[5]" = "GPP_CLK_OFF" register "gpp_clk_config[6]" = "GPP_CLK_OFF" + register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3