From 0f47ff1be5a16c8de1995617830ec8fedbbb4197 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Wed, 4 Sep 2019 13:49:07 +0800 Subject: mb/google/drallion: Dynamicly disable memory channel Disable memory channel by HW strap pin. Using for factory debug. BUG=b:139773082 BRANCH=N/A TEST=Rework HW strap pin and check /proc/mem_info Signed-off-by: Eric Lai Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35241 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/google/drallion/variants/drallion/gpio.c | 7 +++++++ .../google/drallion/variants/drallion/include/variant/gpio.h | 4 ++++ 2 files changed, 11 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 154fc5a7f2..f0fc55e8d4 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -286,4 +286,11 @@ void variant_mainboard_post_init_params(FSPM_UPD *mupd) FSP_M_CONFIG *fsp_m_cfg = &mupd->FspmConfig; if (fsp_m_cfg->PchIshEnable) fsp_m_cfg->PchIshEnable = is_ish_device_enabled(); + + /* + * Disable memory channel by HW strap pin, HW default is enable + * 0: Enable both DIMMs, 3: Disable both DIMMs + */ + mupd->FspmConfig.DisableDimmChannel0 = gpio_get(DDR_CH0_EN) ? 0 : 3; + mupd->FspmConfig.DisableDimmChannel1 = gpio_get(DDR_CH1_EN) ? 0 : 3; } diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index 251b40e0d0..219e0c4b37 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -28,6 +28,10 @@ /* Sensor detection pin */ #define SENSOR_DET_360 GPP_H5 +/* DDR channel enable pin */ +#define DDR_CH0_EN GPP_F1 +#define DDR_CH1_EN GPP_F2 + /* Memory configuration board straps */ #define GPIO_MEM_CONFIG_0 GPP_F12 #define GPIO_MEM_CONFIG_1 GPP_F13 -- cgit v1.2.3