From 09703f64940a66345f27d28c0e339c7ac1864b54 Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Sat, 16 Sep 2017 02:01:13 +0530 Subject: mb/google/{poppy,soraka}: Enable LTR for Root port Enable LTR for Root port 0, where wifi card is connected. BUG=b:65570878 TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported by AER driver for root port 0. Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014 Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/21548 Tested-by: build bot (Jenkins) Reviewed-by: Rajat Jain Reviewed-by: Furquan Shaikh --- src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 4 +++- src/mainboard/google/poppy/variants/soraka/devicetree.cb | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 0bd2efc92c..61b16e65f1 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -153,7 +153,9 @@ chip soc/intel/skylake # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting - register PcieRpAdvancedErrorReporting[0] = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + # RP 1, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index ee9c5b7780..fa16ae02e5 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -153,7 +153,9 @@ chip soc/intel/skylake # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting - register PcieRpAdvancedErrorReporting[0] = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + # RP 1, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port -- cgit v1.2.3