From 6dbf4c8f031a13b1235c60eaca5757ce71aafa68 Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Wed, 26 Aug 2020 13:59:12 +0800 Subject: mb/google/vilboz: update telemetry settings update the telemetry setting for second SDLE testing(for APU power adjusting). Those values are used to power calibration the APU power and achieving the best performance. BUG=b:160698427 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Chris Wang Change-Id: I4cf5b8f090befd6a3c4990f44f2f200bc66aa1f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44804 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/variants/vilboz/overridetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google/zork/variants/vilboz') diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index d415de59c9..3d9ff7c01b 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -18,10 +18,10 @@ chip soc/amd/picasso # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope" = "32453" #mA - register "telemetry_vddcr_vdd_offset" = "168" - register "telemetry_vddcr_soc_slope" = "22644" #mA - register "telemetry_vddcr_soc_offset" = "-70" + register "telemetry_vddcr_vdd_slope" = "32643" #mA + register "telemetry_vddcr_vdd_offset" = "208" + register "telemetry_vddcr_soc_slope" = "22742" #mA + register "telemetry_vddcr_soc_offset" = "-83" # USB OC pin mapping register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 -- cgit v1.2.3