From 9f47a053a35ea11f0906760bca023f4f99241635 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 24 Jun 2020 00:03:06 -0700 Subject: mb/google/zork: Move PCIE_RST1_L deassertion to happen early for dalboz This change moves PCIE_RST1_L deassertion to happen as part of variant_pcie_power_reset_configure() instead of variant_romstage_entry() since romstage is guaranteed to run 100ms+ after PP3300_NVME is enabled. This is one of the first things that coreboot on x86 does as part of early mainboard configuration. Additionally, this change also drops deassertion of PCIE_RST0_L on bid 1 for dalboz since PCIE_RST0_L is already deasserted much earlier in the boot flow. BUG=b:152582706 Signed-off-by: Furquan Shaikh Change-Id: Ib734aa6ff664268e68388b1997ddce676504f8d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261996 Reviewed-by: Aaron Durbin Commit-Queue: Aaron Durbin Tested-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/42936 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- .../google/zork/variants/dalboz/Makefile.inc | 2 -- .../google/zork/variants/dalboz/romstage.c | 25 ---------------------- 2 files changed, 27 deletions(-) delete mode 100644 src/mainboard/google/zork/variants/dalboz/romstage.c (limited to 'src/mainboard/google/zork/variants/dalboz') diff --git a/src/mainboard/google/zork/variants/dalboz/Makefile.inc b/src/mainboard/google/zork/variants/dalboz/Makefile.inc index a616e2fdc0..51d19fe9ba 100644 --- a/src/mainboard/google/zork/variants/dalboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/dalboz/Makefile.inc @@ -2,7 +2,5 @@ subdirs-y += ./spd -romstage-y += romstage.c - ramstage-y += gpio.c ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/dalboz/romstage.c b/src/mainboard/google/zork/variants/dalboz/romstage.c deleted file mode 100644 index 42e36c4525..0000000000 --- a/src/mainboard/google/zork/variants/dalboz/romstage.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include -#include -#include -#include - -void variant_romstage_entry(void) -{ - uint32_t board_version; - - if (google_chromeec_cbi_get_board_version(&board_version)) - board_version = 1; - - if (board_version < 2) { - /* SET PCIE_RST0_L HIGH */ - gpio_set(WIFI_PCIE_RESET_L, 1); - } else { - /* SET PCIE_RST1_L HIGH */ - gpio_set(PCIE_RST1_L, 1); - } -} -- cgit v1.2.3