From 4100f2b97c315ec92f37f3392b733ee0b6f52887 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 27 Feb 2018 10:30:34 -0800 Subject: mainboard/google/zoombini/variant/meowth: enable speed shift BUG=b:73817825,b:69011806 BRANCH=master TEST=Build and flash to meowth, verify cpufreq shows up in kernel for all cores : localhost ~ # find / -name "cpufreq" /sys/devices/system/cpu/cpu3/cpufreq /sys/devices/system/cpu/cpu1/cpufreq /sys/devices/system/cpu/cpufreq /sys/devices/system/cpu/cpu2/cpufreq /sys/devices/system/cpu/cpu0/cpufreq /sys/module/cpufreq /usr/share/laptop-mode-tools/modules/cpufreq Change-Id: I63242b2b049e37167c0d3b8eab630cb6e15a75fd Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/24902 Reviewed-by: Lijian Zhao Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/zoombini/variants/meowth/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/zoombini') diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index c0e4ac3317..cc0d3926a9 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -70,6 +70,9 @@ chip soc/intel/cannonlake register "PchHdaAudioLinkSsp0" = "1" register "PchHdaAudioLinkSsp1" = "1" + # Enable cpufreq + register "speed_shift_enable" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- cgit v1.2.3