From c4986eb7f4eee0f305c6a6f05b45effae152062c Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 9 May 2018 14:55:09 +0530 Subject: soc/intel/common/block: Add common chip config block Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh Reviewed-by: Hannah Williams Tested-by: build bot (Jenkins) --- .../zoombini/variants/baseboard/devicetree.cb | 19 +++++++++---- .../google/zoombini/variants/meowth/devicetree.cb | 32 ++++++++++++++-------- 2 files changed, 34 insertions(+), 17 deletions(-) (limited to 'src/mainboard/google/zoombini/variants') diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index 6f70dfba2a..479f28015a 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -25,11 +25,20 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "1" - # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM - # communication before memory is up. - register "gspi[0]" = "{ - .speed_mhz = 1, - .early_init = 1, + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, }" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 7d89b78e8b..adeedea701 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -34,11 +34,26 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "1" - # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM - # communication before memory is up. - register "gspi[0]" = "{ - .speed_mhz = 1, - .early_init = 1, + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Touchscreen Digitizer | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .rise_time_ns = 98, + .fall_time_ns = 38, + }, }" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" @@ -55,13 +70,6 @@ chip soc/intel/cannonlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" - # Touchscreen Digitizer - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST_PLUS, - .rise_time_ns = 98, - .fall_time_ns = 38, - }" - register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkSsp0" = "1" register "PchHdaAudioLinkSsp1" = "1" -- cgit v1.2.3