From 45b6080561748fe579c8ee901811cf4043383c2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 8 Jan 2022 20:47:11 +0100 Subject: soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 3 +++ src/mainboard/google/volteer/variants/voema/overridetree.cb | 1 + 2 files changed, 4 insertions(+) (limited to 'src/mainboard/google/volteer') diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index a93a38a830..1fa7d2fa5f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -120,11 +120,13 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" + register "PcieRpSlotImplemented[8]" = "1" # Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" register "HybridStorageMode" = "0" + register "PcieRpSlotImplemented[10]" = "1" # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" @@ -138,6 +140,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[6]" = "1" # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 8fdc0674db..808127f86d 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -15,6 +15,7 @@ chip soc/intel/tigerlake register "PcieRpEnable[6]" = "0" register "PcieRpLtrEnable[6]" = "0" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + register "PcieRpSlotImplemented[6]" = "1" # Disable SD Card PCIE 8 register "PcieRpEnable[7]" = "0" -- cgit v1.2.3