From ae10d8119ee235b8421227ba0fcecd6e8ac189d6 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Fri, 11 Jun 2021 18:03:51 -0700 Subject: mb/google/volteer/var/terrador: change GPP_B2 to PLTRST Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I1214246bb1318869e9b6f57cb6a7e74bbe6574cc Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/55439 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/variants/terrador/gpio.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'src/mainboard/google/volteer/variants') diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index 66bc15b8be..69760c13ff 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -25,7 +25,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPO(GPP_A22, 1, DEEP), /* B2 : VRALERT# ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_B2, 1, DEEP), + PAD_CFG_GPO(GPP_B2, 1, PLTRST), /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ @@ -184,11 +184,6 @@ const struct pad_config *variant_override_gpio_table(size_t *num) /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* C8 : UART0 RX */ - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), - /* C9 : UART0 TX */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), - /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ @@ -198,7 +193,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_A17, NONE, DEEP), /* B2 : VRALERT# ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_B2, 1, DEEP), + PAD_CFG_GPO(GPP_B2, 1, PLTRST), /* B11 : PMCALERT# ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ @@ -212,6 +207,10 @@ static const struct pad_config early_gpio_table[] = { /* C0 : SMBCLK ==> EN_PP3300_WLAN */ PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ -- cgit v1.2.3