From 6df0c67c090d8f4243af5cb827b4567f5e2df99e Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 29 Dec 2020 19:02:59 +0800 Subject: mb/google/volteer/var/voema: Update Aux settings for Port 0 On Voema port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. BUG=b:176462544 TEST=tested on voema Signed-off-by: David Wu Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak Reviewed-by: Caveh Jalali --- src/mainboard/google/volteer/variants/voema/overridetree.cb | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/volteer/variants') diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index daea4327b8..ff6b64bfac 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -5,6 +5,10 @@ chip soc/intel/tigerlake # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + # Disable WLAN PCIE 7 register "PcieRpEnable[6]" = "0" register "PcieRpLtrEnable[6]" = "0" @@ -105,8 +109,6 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "5" register "usb3_port_number" = "1" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn -- cgit v1.2.3