From 2f78ce0995a6dd0630802a918438c4d3b1c328fc Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 16 Feb 2021 19:06:16 -0800 Subject: mb/google/volteer: Fix FPMCU pwr/rst gpio handling 1. No gpio control in bootblock 2. Power on and then deassert reset at the end of ramstage gpio 3. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #3 and wrapping around to #2. This change affects the following volteer variants that include an FPMCU: 1. Drobit 2. Eldrid 3. Elemi 4. Halvor 5. Malefor 6. Terrador 7. Trondo 8. Voema 9. Volteer2 10. Voxel BUG=b:178094376 TEST=none Change-Id: Ib51815349cea299907c10d6c56c27bd239e499e7 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/50828 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Tim Wawrzynczak --- .../google/volteer/variants/voxel/Makefile.inc | 1 + src/mainboard/google/volteer/variants/voxel/gpio.c | 21 +++++++++++++++++---- .../google/volteer/variants/voxel/ramstage.c | 20 ++++++++++++++++++++ 3 files changed, 38 insertions(+), 4 deletions(-) create mode 100644 src/mainboard/google/volteer/variants/voxel/ramstage.c (limited to 'src/mainboard/google/volteer/variants/voxel') diff --git a/src/mainboard/google/volteer/variants/voxel/Makefile.inc b/src/mainboard/google/volteer/variants/voxel/Makefile.inc index b0bfc567ff..3488dc6cc2 100644 --- a/src/mainboard/google/volteer/variants/voxel/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voxel/Makefile.inc @@ -5,3 +5,4 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c index 6be86dedc4..4ec02c5167 100644 --- a/src/mainboard/google/volteer/variants/voxel/gpio.c +++ b/src/mainboard/google/volteer/variants/voxel/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -18,8 +19,6 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP), /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ @@ -80,8 +79,6 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ PAD_CFG_GPI(GPP_D0, NONE, DEEP), @@ -279,3 +276,19 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* GPIO settings before entering S5 */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), /* EN_FP_PWR */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/volteer/variants/voxel/ramstage.c b/src/mainboard/google/volteer/variants/voxel/ramstage.c new file mode 100644 index 0000000000..b198992824 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void variant_ramstage_init(void) +{ + /* + * Assert FPMCU reset and enable power to FPMCU, + * wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while. + */ + gpio_output(GPP_C23, 0); + gpio_output(GPP_A21, 1); + mdelay(1); + gpio_output(GPP_C23, 1); +} -- cgit v1.2.3