From 90e56267cf158af3d692b709f7f41120130234a4 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Fri, 14 Aug 2020 21:18:27 -0700 Subject: mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Volteer EVT board. Signed-off-by: John Zhao Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/44501 Reviewed-by: Caveh Jalali Reviewed-by: Wonkyu Kim Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/volteer2/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google/volteer/variants/volteer2/overridetree.cb') diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 76a5b87f3e..3036a48f21 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -2,6 +2,8 @@ chip soc/intel/tigerlake register "TcssAuxOri" = "1" register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" device domain 0 on device pci 15.0 on -- cgit v1.2.3