From 9e2761fe2ba3f9a193885a44fb045be60dc7b2b1 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 22 Dec 2020 13:24:37 +0800 Subject: mb/google/volteer/var/voema: Disable PCIe 7 and 8 for WLAN and SD card Based on latest schematic, disable PCIe 7 and 8 for WLAN and SD card. BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu Change-Id: I2a4658a382c094c2a5b16b7acaf464f54e9897b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48845 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/variants/voema/overridetree.cb | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/volteer/variants/voema') diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 8d05c3213f..f612beb3a1 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -5,8 +5,15 @@ chip soc/intel/tigerlake # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033" - # Disable SRCCLKREQ1# and SRCCLKREQ3# + # Disable WLAN PCIE 7 + register "PcieRpEnable[6]" = "0" + register "PcieRpLtrEnable[6]" = "0" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + + # Disable SD Card PCIE 8 + register "PcieRpEnable[7]" = "0" + register "PcieRpLtrEnable[7]" = "0" + register "PcieRpHotPlug[7]" = "0" register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" device domain 0 on -- cgit v1.2.3