From 77a23d10bfbc928812bbe6ba5426ca461a64ff26 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 27 Oct 2020 16:13:17 +0800 Subject: mb/google/volteer/var/terrador: Enable SaGv support Enable SaGv for terrador. BUG=b:171763116 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46841 Tested-by: build bot (Jenkins) Reviewed-by: Derek Huang Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Fagerburg --- src/mainboard/google/volteer/variants/terrador/overridetree.cb | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mainboard/google/volteer/variants/terrador') diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index fbf724f601..d2e2d0b323 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -14,8 +14,6 @@ chip soc/intel/tigerlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 - register "SaGv" = "SaGv_Disabled" - # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" -- cgit v1.2.3