From 5b1f335ef8aed95e01f040bc7074fb00acc8ab7e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 26 Mar 2020 15:36:19 -0700 Subject: soc/intel/tigerlake: Reorganize memory initialization support This change reorganizes memory initialization code for LPDDR4x on TGL to allow sharing of code when adding support for other memory types. In follow-up changes, support for DDR4 will be added. 1. It adds configuration for memory topology which is currently only MEMORY_DOWN, however DDR4 requires more topologies to be supported. 2. spd_info structure is organized to allow mixed topologies as well. 3. DQ/DQS maps are organized to reflect hardware configuration. TEST=Verified that volteer still boots and memory initialization is successful. Signed-off-by: Furquan Shaikh Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- .../google/volteer/variants/malefor/memory.c | 63 ++++++++++++++-------- 1 file changed, 42 insertions(+), 21 deletions(-) (limited to 'src/mainboard/google/volteer/variants/malefor') diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 75ac762a47..4e5313db36 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -3,38 +3,59 @@ #include -static const struct mb_lpddr4x_cfg malefor_memcfg = { +static const struct lpddr4x_cfg malefor_memcfg = { /* DQ byte map */ .dq_map = { - { 3, 1, 0, 2, 4, 6, 7, 5, /* Byte 0 */ - 12, 13, 14, 15, 8, 9, 10, 11 }, /* Byte 1 */ - { 0, 7, 1, 6, 2, 4, 3, 5, /* Byte 2 */ - 8, 15, 14, 9, 13, 10, 12, 11 }, /* Byte 3 */ - { 3, 2, 0, 1, 4, 5, 6, 7, /* Byte 4 */ - 12, 13, 15, 14, 8, 9, 10, 11 }, /* Byte 5 */ - { 6, 0, 1, 7, 5, 4, 2, 3, /* Byte 6 */ - 15, 14, 8, 9, 10, 12, 11, 13 }, /* Byte 7 */ - { 5, 0, 1, 3, 4, 2, 7, 6, /* Byte 0 */ - 11, 14, 13, 12, 8, 9, 15, 10 }, /* Byte 1 */ - { 3, 4, 2, 5, 0, 6, 1, 7, /* Byte 2 */ - 13, 12, 11, 10, 14, 15, 9, 8 }, /* Byte 3 */ - { 3, 2, 1, 0, 5, 4, 7, 6, /* Byte 4 */ - 12, 13, 15, 14, 8, 11, 9, 10 }, /* Byte 5 */ - { 3, 4, 2, 5, 1, 0, 7, 6, /* Byte 6 */ - 15, 14, 9, 8, 12, 10, 11, 13 } /* Byte 7 */ + [0] = { + { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, }, /* DQS CPU<>DRAM map */ .dqs_map = { - /* Ch 0 1 2 3 */ - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ }, .ect = 0, /* Disable Early Command Training */ }; -const struct mb_lpddr4x_cfg *variant_memory_params(void) +const struct lpddr4x_cfg *variant_memory_params(void) { return &malefor_memcfg; } -- cgit v1.2.3