From 028e527cbd880078bc195fbf62e49732c7523904 Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Fri, 31 Jul 2020 04:30:24 -0700 Subject: mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_table GPP_D16 is routed to the main power enable pin on several PCIe SD card controllers on SD daughterboards. We should enable the power to these chips as early as possible so they can participate in PCIe enumeration. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be Signed-off-by: Caveh Jalali Reviewed-on: https://review.coreboot.org/c/coreboot/+/44117 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Nick Vaccaro --- src/mainboard/google/volteer/variants/malefor/gpio.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/volteer/variants/malefor') diff --git a/src/mainboard/google/volteer/variants/malefor/gpio.c b/src/mainboard/google/volteer/variants/malefor/gpio.c index cdffb60dd9..22dec73eac 100644 --- a/src/mainboard/google/volteer/variants/malefor/gpio.c +++ b/src/mainboard/google/volteer/variants/malefor/gpio.c @@ -183,6 +183,9 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPO(GPP_E12, 1, DEEP), -- cgit v1.2.3