From e928391f74aa75fb92a701a8586c4b9050f2a964 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Sat, 31 Oct 2020 01:24:43 +0800 Subject: mb/google/volteer/var/elemi: enable Genesys Logic GL9763E Enable Genesys GL9763E as PCI-to-eMMC bridge. BUG=b:171467336 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen Change-Id: I858c12151df5b6fc19132869317edfa1b090335d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47040 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/variants/elemi/overridetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/google/volteer/variants/elemi/overridetree.cb') diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 4afc795afd..d4c40f9795 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -6,6 +6,13 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" + # Enable EMMC PCIE 5 using clk 5 + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + register "PcieClkSrcUsage[5]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -184,6 +191,7 @@ chip soc/intel/tigerlake device generic 0 on end end end + device ref pcie_rp5 on end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. -- cgit v1.2.3