From b8bfe142c6bbaf3674e9d0ff70b42ca32bcb4df4 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 21 Apr 2020 17:07:57 -0700 Subject: mb/google/voteer: Enable DevSlp for SATA port1 BUG=b:152893285 BRANCH=none TEST=Build and boot to OS volteer with Intel SATA and reboot from OS console Signed-off-by: Wonkyu Kim Change-Id: Ibed8f8c445bf2ac2290ffb670d8dfb83fc960438 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40584 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/volteer/variants/baseboard/devicetree.cb') diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 12ae87afcd..b68966331c 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -77,6 +77,7 @@ chip soc/intel/tigerlake register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "1" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- cgit v1.2.3