From 7d6bc60db9427f029f990002870e40541601a209 Mon Sep 17 00:00:00 2001
From: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Date: Fri, 8 May 2020 19:22:07 +0530
Subject: tigerlake: enable DPTF functionality for volteer

Enable DPTF functionality for volteer platform

BRANCH=None
BUG=b:149722146
TEST=Built and tested on volteer system

Change-Id: I385fb409ccd291d97369295ff99f21c9430880f9
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41427
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src/mainboard/google/volteer/variants/baseboard/devicetree.cb')

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 5d5dcc4b70..25b42c74f7 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -170,6 +170,16 @@ chip soc/intel/tigerlake
 	# Enable S0ix
 	register "s0ix_enable" = "1"
 
+	# Enable DPTF
+	register "dptf_enable" = "1"
+
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 60,
+	}"
+
+	register "Device4Enable" = "1"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
-- 
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