From 5fdf2760a5952df22e5b331bc4f62082d8cec1bc Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 28 Jul 2020 12:51:53 -0700 Subject: mb/google/volteer: Update TCSS D3Hot and D3Cold configuration It is expected TCSS D3Hot is enabled. D3Cold configuration is through SoC stepping determination. D3Cold is disabled on pre-QS platform and enabled on QS platform. BUG=None TEST=Verified both of TCSS D3Hot and D3Cold configuration on Volteer. Signed-off-by: John Zhao Change-Id: I9a8b838dcb449ca78d15b18543d97d84b59417ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/44004 Reviewed-by: Caveh Jalali Reviewed-by: Divya S Sasidharan Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mainboard/google/volteer/variants/baseboard/devicetree.cb') diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 0e8ad3e17a..53bbe5a0c0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -170,10 +170,6 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[6]" = "0x09000000" register "IomTypeCPortPadCfg[7]" = "0x09000000" - # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "0" - # DP port register "DdiPortAConfig" = "1" # eDP register "DdiPortBConfig" = "0" -- cgit v1.2.3