From 40b5358c2accfb329b492a1b861b067c8303c6c5 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Mon, 21 Dec 2020 14:57:50 -0800 Subject: mainboard/volteer: Configure UsbTcPortEn value The default value is not sufficient to correctly configure the Type-C ports as it has all ports disabled by default. On Volteer ports 0 and 1 are enabled so setting this value to 0x3 and correctly keeping the IomPortPadCfg values at 0 for ports that have a retimer and ports that are not configured. These values were set to 0x90000000 to avoid s0ix issues which arose from the UsbTcPortEn value being incorrect. BUG=b:159151238 BRANCH=firmware-volteer-13672.B TEST=Built image for Voxel and verified that s0ix cycles complete without any issues Change-Id: Ib4f2bd0f68debd4e97ccaab9e1d8a873dc4e4d9f Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/c/coreboot/+/48814 Reviewed-by: Tim Wawrzynczak Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'src/mainboard/google/volteer/variants/baseboard/devicetree.cb') diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 01bbf1e06b..d74476af16 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -221,16 +221,9 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkSndwEnable[1]" = "0" # TCSS USB3 + register "UsbTcPortEn" = "0x3" register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" - register "IomTypeCPortPadCfg[0]" = "0x09000000" - register "IomTypeCPortPadCfg[1]" = "0x09000000" - register "IomTypeCPortPadCfg[2]" = "0x09000000" - register "IomTypeCPortPadCfg[3]" = "0x09000000" - register "IomTypeCPortPadCfg[4]" = "0x09000000" - register "IomTypeCPortPadCfg[5]" = "0x09000000" - register "IomTypeCPortPadCfg[6]" = "0x09000000" - register "IomTypeCPortPadCfg[7]" = "0x09000000" # DP port register "DdiPortAConfig" = "1" # eDP -- cgit v1.2.3