From 2c807ff6fe085b645d6da42a0472f2c31d19ec29 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Thu, 18 Jun 2020 00:25:51 -0700 Subject: mb/google/volteer: Disable D3Cold for TCSS along with pass through mode The pass through mode (SW CM) RTD3 is not supported until QS platform. D3Cold is needed to be disabled along with upstream TBT firmware signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix. This temporary patch will need to be reverted once PM RTD3 support is validated on QS platform. BUG=b:159050315 TEST=Verfiy PM S0ix along with upstream TBT firmware. Signed-off-by: John Zhao Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42504 Reviewed-by: Tim Wawrzynczak Reviewed-by: Wonkyu Kim Reviewed-by: Divya Sasidharan Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/volteer/variants/baseboard/devicetree.cb') diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index f2e427f0bb..9732aa84a4 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -159,7 +159,7 @@ chip soc/intel/tigerlake # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" + register "TcssD3ColdEnable" = "0" # DP port register "DdiPortAConfig" = "1" # eDP -- cgit v1.2.3