From e4d438e8dcf691e8ef65f32415e9176b11c85fa2 Mon Sep 17 00:00:00 2001 From: ZhengShunQian Date: Thu, 22 Oct 2015 10:33:13 +0800 Subject: google/veyron_emile: Add new board of veyron This is a copy of mickey and renamed. CQ-DEPEND=CL:306967 BUG=chrome-os-partner:46658 TEST=build coreboot BRANCH=veyron Change-Id: I9e1232f3f1334ec747a5beb52f214635a7ab08ae Signed-off-by: Patrick Georgi Original-Commit-Id: 9316a9ec27d5799e290add1e5818f4449b680fde Original-Change-Id: I906de7bbc8b8e110e0774c14ec636a327230b325 Original-Signed-off-by: ZhengShunQian Original-Reviewed-on: https://chromium-review.googlesource.com/307620 Original-Commit-Ready: David Hendricks Original-Tested-by: David Hendricks Original-Tested-by: Shunqian Zheng Original-Reviewed-by: David Hendricks Reviewed-on: http://review.coreboot.org/12394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- .../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc (limited to 'src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc') diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc new file mode 100644 index 0000000000..00dc549161 --- /dev/null +++ b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Hynix H9CCNNN8GTMLAR chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 14, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, -- cgit v1.2.3