From 09ab856c85b59a04bb14146533d19edd4ccf1467 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 16 Jan 2015 12:08:38 -0800 Subject: Danger: Initial mainboard import This adds a directory with files copied over from Brain along with build-related changes so that emerge-veyron_danger works. The next patch will account for other differences. BUG=none BRANCH=none TEST=emerge-veyron_danger coreboot works Change-Id: I7ebd431cd48e257dfa761d32013d0e251b4f155d Signed-off-by: Stefan Reinauer Original-Commit-Id: a0f7d2f96540df6fdcd7a99d9e0fa02bbc6c1f73 Original-Signed-off-by: David Hendricks Original-Change-Id: Id265a7715f07a647a449f00097bf40f7c9b4c068 Original-Reviewed-on: https://chromium-review.googlesource.com/241711 Original-Reviewed-by: Julius Werner Reviewed-on: http://review.coreboot.org/9646 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/mainboard/google/veyron_danger/bootblock.c | 78 ++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 src/mainboard/google/veyron_danger/bootblock.c (limited to 'src/mainboard/google/veyron_danger/bootblock.c') diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c new file mode 100644 index 0000000000..610c23e4de --- /dev/null +++ b/src/mainboard/google/veyron_danger/bootblock.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board.h" + +void bootblock_mainboard_early_init() +{ + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) { + assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); + writel(IOMUX_UART2, &rk3288_grf->iomux_uart2); + } + +} + +void bootblock_mainboard_init(void) +{ + gpio_output(GPIO(7, A, 0), 1); /* Power LED */ + + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ + setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */ + i2c_init(CONFIG_PMIC_BUS, 400*KHz); + + /* Slowly raise to max CPU voltage to prevent overshoot */ + rk808_configure_buck(1, 1200); + udelay(175);/* Must wait for voltage to stabilize,2mV/us */ + rk808_configure_buck(1, 1400); + udelay(100);/* Must wait for voltage to stabilize,2mV/us */ + rkclk_configure_cpu(); + + if (rkclk_was_watchdog_reset()) { + printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n"); + hard_reset(); + } + + /* i2c1 for tpm */ + writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); + i2c_init(1, 400*KHz); + + /* spi2 for firmware ROM */ + writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); + writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz); + + setup_chromeos_gpios(); +} -- cgit v1.2.3