From 2cd9c05dc10462c105d889cecc148b5d87ac53fb Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Tue, 12 Jan 2016 22:01:13 -0800 Subject: google/veyron_*: Add dual-rank 2GB Hynix module to SDRAM configs This is a follow-up to CL:320623 to make veyron DRAM configs uniform (except for Rialto). As discussed in chrome-os-partner:43626, the mr[3] value and ODT are set diffently for Mickey, thus the .inc files for other boards have mr[3] = 1 and ODT disabled. BUG=none BRANCH=veyron TEST=compile tested for veyron Change-Id: I61798cfef779b0a3a510fd354ab53ffc63ca6c95 Signed-off-by: Patrick Georgi Original-Commit-Id: 3b7cea6331bcec8aba09a204060e093d3dd732cb Original-Signed-off-by: David Hendricks Original-Change-Id: Iacf821645a2dcceaed1c1c42e3e1b1c312b31eab Original-Reviewed-on: https://chromium-review.googlesource.com/321870 Original-Reviewed-by: Julius Werner Reviewed-on: https://review.coreboot.org/13109 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/mainboard/google/veyron/sdram_configs.c | 2 +- .../sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc | 78 ++++++++++++++++++++++ 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc (limited to 'src/mainboard/google/veyron') diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index 66e839ed70..aaa0bf34d5 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -24,7 +24,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ +#include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */ diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc new file mode 100644 index 0000000000..8d22e6c55a --- /dev/null +++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc @@ -0,0 +1,78 @@ +{ + /* Hynix H9CCNNNBPTBLBR-NUD chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 2, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, -- cgit v1.2.3