From 739df1b2c2e334dfd03b81393cf1e95f0cb98607 Mon Sep 17 00:00:00 2001 From: huang lin Date: Wed, 27 Aug 2014 17:07:42 +0800 Subject: rk3288: update romstage & mainboard BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I877b4bf741f45f6cfd032ad5018a60e8a1453622 Signed-off-by: Patrick Georgi Original-Commit-Id: 640da5ad5597803c62d9374a1a48832003077723 Original-Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb Original-Signed-off-by: Jeffy Chen Original-Signed-off-by: huang lin Original-Reviewed-on: https://chromium-review.googlesource.com/209469 Original-Reviewed-by: Julius Werner Original-Tested-by: Julius Werner Reviewed-on: http://review.coreboot.org/8867 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/veyron/romstage.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google/veyron/romstage.c') diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c index 5831fde095..e1062ca9e9 100644 --- a/src/mainboard/google/veyron/romstage.c +++ b/src/mainboard/google/veyron/romstage.c @@ -27,17 +27,34 @@ #include #include #include +#include #include +#include +#include "timer.h" void main(void) { - console_init(); - +#if CONFIG_COLLECT_TIMESTAMPS + uint64_t start_romstage_time; + uint64_t before_dram_time; + uint64_t after_dram_time; + uint64_t base_time = timestamp_get(); + start_romstage_time = timestamp_get(); +#endif /* used for MMU and CBMEM setup, in MB */ u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); u32 dram_size = CONFIG_DRAM_SIZE_MB; u32 dram_end = dram_start + dram_size; + + console_init(); + +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); +#endif sdram_init(get_sdram_config()); +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = timestamp_get(); +#endif mmu_init(); /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start, DCACHE_OFF); @@ -49,10 +66,18 @@ void main(void) /* The space above DRAM is uncached. */ if (dram_end < 4096) mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); - mmu_disable_range(0, 1); dcache_mmu_enable(); + setup_chromeos_gpios(); + cbmem_initialize_empty(); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time); + timestamp_add(TS_AFTER_INITRAM, after_dram_time); + timestamp_add_now(TS_END_ROMSTAGE); +#endif run_ramstage(); } -- cgit v1.2.3