From af4bd5633debc8838b563c3fadd96e2b4b060ab5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 28 Dec 2021 13:05:56 +0100 Subject: sb/intel: Use `bool` for PCIe coalescing option Retype the `pcie_port_coalesce` devicetree options and related variables to better reflect their bivalue (boolean) nature. Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416 Reviewed-by: Felix Held Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/mainboard/google/stout/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/stout') diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index ad700cee29..b38adaf148 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -61,7 +61,7 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x0001C1611" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 -- cgit v1.2.3