From b7ecf6d83047e70ed5846ac35833a04983318b9c Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 13 Mar 2013 17:13:32 -0700 Subject: Add support for "Stout" Chromebook We're happy to announce coreboot support for the "Stout" Chromebook, a.k.a Lenovo X131e Chromebook. Change-Id: I9b995f8d0dd48e41c788b7c3d35b4fac5840e425 Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/2636 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/mainboard/google/stout/acpi/chromeos.asl | 27 +++++++ src/mainboard/google/stout/acpi/ec.asl | 24 ++++++ src/mainboard/google/stout/acpi/mainboard.asl | 46 +++++++++++ src/mainboard/google/stout/acpi/platform.asl | 88 ++++++++++++++++++++++ .../google/stout/acpi/sandybridge_pci_irqs.asl | 73 ++++++++++++++++++ src/mainboard/google/stout/acpi/superio.asl | 27 +++++++ src/mainboard/google/stout/acpi/thermal.asl | 88 ++++++++++++++++++++++ src/mainboard/google/stout/acpi/video.asl | 43 +++++++++++ 8 files changed, 416 insertions(+) create mode 100644 src/mainboard/google/stout/acpi/chromeos.asl create mode 100644 src/mainboard/google/stout/acpi/ec.asl create mode 100644 src/mainboard/google/stout/acpi/mainboard.asl create mode 100644 src/mainboard/google/stout/acpi/platform.asl create mode 100644 src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl create mode 100644 src/mainboard/google/stout/acpi/superio.asl create mode 100644 src/mainboard/google/stout/acpi/thermal.asl create mode 100644 src/mainboard/google/stout/acpi/video.asl (limited to 'src/mainboard/google/stout/acpi') diff --git a/src/mainboard/google/stout/acpi/chromeos.asl b/src/mainboard/google/stout/acpi/chromeos.asl new file mode 100644 index 0000000000..b69aff1bf4 --- /dev/null +++ b/src/mainboard/google/stout/acpi/chromeos.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(OIPG, Package() { + // No GPIO for recovery mode, developer mode, or firmware write protect + // on stout - note: all virtual pins are active HIGH polarity on stout. + Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button + Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button + Package() { 0x003, 0, 7, "PantherPoint" }, // firmware write protect +}) + diff --git a/src/mainboard/google/stout/acpi/ec.asl b/src/mainboard/google/stout/acpi/ec.asl new file mode 100644 index 0000000000..b807894aca --- /dev/null +++ b/src/mainboard/google/stout/acpi/ec.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include "../ec.h" + +/* ACPI code for EC functions */ +#include diff --git a/src/mainboard/google/stout/acpi/mainboard.asl b/src/mainboard/google/stout/acpi/mainboard.asl new file mode 100644 index 0000000000..4ea4a09766 --- /dev/null +++ b/src/mainboard/google/stout/acpi/mainboard.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId("PNP0C0D")) + Name (_PRW, Package() {0x18, 4}) + + Method (_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.HPLD, \LIDS) + Return (\LIDS) + } + + Method (_PSW, 1) + { + // Enable/Disable LID as a wake source + Store (Arg0, \_SB.PCI0.LPCB.EC0.HWLO) + } + } + + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/google/stout/acpi/platform.asl b/src/mainboard/google/stout/acpi/platform.asl new file mode 100644 index 0000000000..a90a16eb30 --- /dev/null +++ b/src/mainboard/google/stout/acpi/platform.asl @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Notify EC to enter S3 + Store(0x01, \_SB.PCI0.LPCB.EC0.S3FG) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Update AC status */ + Store (\_SB.PCI0.LPCB.EC0.ACPW, Local0) + if (LNotEqual (Local0, \PWRS)) { + Store (Local0, \PWRS) + Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) + } + + /* Update LID status */ + Store (NOT(\_SB.PCI0.LPCB.EC0.HPLD), Local0) + if (LNotEqual (Local0, \LIDS)) { + Store (Local0, \LIDS) + Notify (\_SB.LID0, 0x80) + } + + Return(Package(){0,0}) +} + diff --git a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000000..7ce8cd85fb --- /dev/null +++ b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 19 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 19 }, + Package() { 0x001cffff, 1, 0, 20 }, + Package() { 0x001cffff, 2, 0, 17 }, + Package() { 0x001cffff, 3, 0, 18 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, + Package() { 0x001fffff, 1, 0, 23 }, + Package() { 0x001fffff, 2, 0, 16 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} + diff --git a/src/mainboard/google/stout/acpi/superio.asl b/src/mainboard/google/stout/acpi/superio.asl new file mode 100644 index 0000000000..feb4210fbc --- /dev/null +++ b/src/mainboard/google/stout/acpi/superio.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include "../ec.h" + +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // Enable PS/2 Mouse + +/* ACPI code for EC SuperIO functions */ +#include diff --git a/src/mainboard/google/stout/acpi/thermal.asl b/src/mainboard/google/stout/acpi/thermal.asl new file mode 100644 index 0000000000..0db4d133ec --- /dev/null +++ b/src/mainboard/google/stout/acpi/thermal.asl @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x03) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 10 seconds + Name (_TSP, 100) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) + { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + // Returns Higher of the two readings for CPU & VGA Temperature + If (LGreater (\_SB.PCI0.LPCB.EC0.TMP2, \_SB.PCI0.LPCB.EC0.TMP1)) + { + // CPU high temperature + Store (\_SB.PCI0.LPCB.EC0.TMP2, Local0) + } + Else + { + // VGA high temperature + Store (\_SB.PCI0.LPCB.EC0.TMP1, Local0) + } + + // If temp less 35 or great then 115, set default 35 + If (Or (LLess (Local0, 35), LGreater (Local0, 115))) + { + Store (35, Local0) + } + + Return (CTOK (Local0)) + } + } +} diff --git a/src/mainboard/google/stout/acpi/video.asl b/src/mainboard/google/stout/acpi/video.asl new file mode 100644 index 0000000000..3ececa912b --- /dev/null +++ b/src/mainboard/google/stout/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + -- cgit v1.2.3