From db9eaf4cb2a2fe65b0d08dc5b47426f7399d6757 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 5 Apr 2013 15:38:12 -0700 Subject: snow/exynos5250: move board-specific power stuff to mainboard dir This moves highly board-specific code out from the Exynos5250 power_init() into Snow's romstage.c. There's no reason the CPU- specific code should care about which PMIC we are using and which bus it is on. Change-Id: I52313177395519cddcab11225fc23d5e50c4c4e3 Signed-off-by: David Hendricks Reviewed-on: http://review.coreboot.org/3034 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Ronald G. Minnich --- src/mainboard/google/snow/romstage.c | 54 ++++++++++++++++++++++++++++++++---- 1 file changed, 49 insertions(+), 5 deletions(-) (limited to 'src/mainboard/google/snow') diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 39069b2d95..ca7ba9c23b 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -35,6 +35,9 @@ #include #include +#include +#include + #include "mainboard.h" #define MMC0_GPIO_PIN (58) @@ -52,6 +55,45 @@ static int board_wakeup_permitted(void) } #endif +static int setup_pmic(void) +{ + int error = 0; + + /* + * We're using CR1616 coin cell battery that is non-rechargeable + * battery. But, BBCHOSTEN bit of the BBAT Charger Register in + * MAX77686 is enabled by default for charging coin cell. + * + * Also, we cannot meet the coin cell reverse current spec. in UL + * standard if BBCHOSTEN bit is enabled. + * + * Disable Coin BATT Charging + */ + error = max77686_disable_backup_batt(); + + error |= max77686_volsetting(PMIC_BUCK2, CONFIG_VDD_ARM_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUCK3, CONFIG_VDD_INT_UV, + REG_ENABLE, MAX77686_UV); + error |= max77686_volsetting(PMIC_BUCK1, CONFIG_VDD_MIF_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUCK4, CONFIG_VDD_G3D_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO2, CONFIG_VDD_LDO2_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO3, CONFIG_VDD_LDO3_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO5, CONFIG_VDD_LDO5_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO10, CONFIG_VDD_LDO10_MV, + REG_ENABLE, MAX77686_MV); + + if (error) + printk(BIOS_CRIT, "%s: Error during PMIC setup\n", __func__); + + return error; +} + static void initialize_s5p_mshc(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ @@ -90,11 +132,13 @@ void main(void) system_clock_init(mem, arm_ratios); console_init(); - /* - * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. - * Also, we should only call power_init() on cold boot. - */ - power_init(); + + i2c_set_early_reg(0x12c60000); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (power_init()) + power_shutdown(); + if (setup_pmic()) + power_shutdown(); if (!mem) { printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); -- cgit v1.2.3