From 3044af7adc652f41670f8de0c3c54bc09f632079 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 1 Aug 2018 13:05:14 -0500 Subject: mb/google,samsung/*: Add LPC TPM chip driver to devicetree With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code] and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver (drivers/pc80/tpm) must be added to devicetree in order to ensure the new acpigen code is used to replace it. Test: boot various google/samsung boards, verify SSDT created with LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/27786 Reviewed-by: Philipp Deppenwiese Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/google/slippy/variants/falco/devicetree.cb | 3 +++ src/mainboard/google/slippy/variants/leon/devicetree.cb | 3 +++ src/mainboard/google/slippy/variants/peppy/devicetree.cb | 3 +++ src/mainboard/google/slippy/variants/wolf/devicetree.cb | 3 +++ 4 files changed, 12 insertions(+) (limited to 'src/mainboard/google/slippy/variants') diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/variants/falco/devicetree.cb index cdf47cf5aa..f2a952070e 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/variants/falco/devicetree.cb @@ -109,6 +109,9 @@ chip northbridge/intel/haswell device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb index b0edb7fa2d..8951e99e39 100644 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ b/src/mainboard/google/slippy/variants/leon/devicetree.cb @@ -114,6 +114,9 @@ chip northbridge/intel/haswell device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb index e9875a66e7..6451d95856 100644 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/devicetree.cb @@ -113,6 +113,9 @@ chip northbridge/intel/haswell device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb index 7655c412a9..2cad23b75c 100644 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb @@ -114,6 +114,9 @@ chip northbridge/intel/haswell device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec # We only have one init function that # we need to call to initialize the -- cgit v1.2.3