From bc24b85e6a1ce040e3d9f505e188c686496b7e29 Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Tue, 26 Jul 2016 11:49:11 -0500
Subject: mainboard/google/slippy: remove unobtainable mainboard

The slippy board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.

Change-Id: I24fb08d9be35b2367e7aa64520ce5778ab861535
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15902
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/mainboard/google/slippy/dsdt.asl | 60 ------------------------------------
 1 file changed, 60 deletions(-)
 delete mode 100644 src/mainboard/google/slippy/dsdt.asl

(limited to 'src/mainboard/google/slippy/dsdt.asl')

diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl
deleted file mode 100644
index 9e5a114938..0000000000
--- a/src/mainboard/google/slippy/dsdt.asl
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define ENABLE_TPM
-
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0
-	"COREv4",	// OEM id
-	"COREBOOT",	// OEM table id
-	0x20110725	// OEM revision
-)
-{
-	// Some generic macros
-	#include "acpi/platform.asl"
-	#include "acpi/mainboard.asl"
-
-	// global NVS and variables
-	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
-
-	// General Purpose Events
-	//#include "acpi/gpe.asl"
-
-	// CPU
-	#include <cpu/intel/haswell/acpi/cpu.asl>
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <northbridge/intel/haswell/acpi/haswell.asl>
-			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
-
-			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-		}
-	}
-
-	// Thermal handler
-	#include "acpi/thermal.asl"
-
-	// Chrome OS specific
-	#include "acpi/chromeos.asl"
-	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
-	// Chipset specific sleep states
-	#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
-}
-- 
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