From b3b27f7dea3ac7170adfbfc7e6d4ca7bde9ab780 Mon Sep 17 00:00:00 2001 From: Robert Zieba Date: Mon, 3 Oct 2022 14:50:55 -0600 Subject: soc/amd/mendocino: Enable GPP clk req disabling for disabled devices Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/skyrim/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/skyrim') diff --git a/src/mainboard/google/skyrim/Makefile.inc b/src/mainboard/google/skyrim/Makefile.inc index 0fa733e293..c1d1108fc3 100644 --- a/src/mainboard/google/skyrim/Makefile.inc +++ b/src/mainboard/google/skyrim/Makefile.inc @@ -6,6 +6,7 @@ romstage-y += port_descriptors.c ramstage-y += mainboard.c ramstage-y += ec.c +ramstage-y += port_descriptors.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c -- cgit v1.2.3