From a08765d2871b891c8da2e8686a0db35b320c96b0 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 5 Feb 2019 14:03:44 -0800 Subject: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads This change uses cnl_configure_pads to configure GPIOs in ramstage so that cannonlake SoC code can re-configure the GPIOs after FSP-S is run. This is just adding a workaround until FSP-S is fixed. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/31251 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Aaron Durbin --- src/mainboard/google/sarien/ramstage.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) (limited to 'src/mainboard/google/sarien') diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index c2dc27daee..96321f8d49 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -24,22 +25,11 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) size_t num_gpios; gpio_table = variant_gpio_table(&num_gpios); - gpio_configure_pads(gpio_table, num_gpios); -} - -/* Workaround FSP issue by reprogramming GPIOs after FSP-S */ -static void mainboard_init(struct device *dev) -{ - const struct pad_config *gpio_table; - size_t num_gpios; - - gpio_table = variant_gpio_table(&num_gpios); - gpio_configure_pads(gpio_table, num_gpios); + cnl_configure_pads(gpio_table, num_gpios); } static void mainboard_enable(struct device *dev) { - dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } -- cgit v1.2.3