From 768cd37bc3aa399488bf299486b46e1b1d4f1da7 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Wed, 26 Dec 2018 19:53:32 -0800 Subject: mb/google/sarien: Add settings for noise mitgation Enable acoustic noise mitgation for sarien platform, the slow slew rates are fast time dived by 8. Signed-off-by: Lijian Zhao Change-Id: I5d38a1e03af08f106e2422a319b34c3fb54bdf28 Reviewed-on: https://review.coreboot.org/c/30448 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/google/sarien/variants/sarien/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard/google/sarien') diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 47abadc5d9..0b8e5c6519 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -33,6 +33,11 @@ chip soc/intel/cannonlake register "dptf_enable" = "1" register "dmipwroptimize" = "1" register "satapwroptimize" = "1" + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "SlowSlewRateForFivr" = "2" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port -- cgit v1.2.3