From 2539a672731e0f8059ce76a11a350a3a0c5ccddf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 5 Sep 2020 13:47:11 +0200 Subject: mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 4 ---- src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 -- 2 files changed, 6 deletions(-) (limited to 'src/mainboard/google/sarien') diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 760e35146e..9a4c6dda10 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -132,8 +132,6 @@ chip soc/intel/cannonlake register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[6]" = "{ .enable = 1, \ @@ -151,8 +149,6 @@ chip soc/intel/cannonlake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 78f024cbf4..a76e2ed2e9 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -139,7 +139,6 @@ chip soc/intel/cannonlake register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Left Type-A Port register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Right Type-A Port 2 - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH @@ -151,7 +150,6 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Left Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Right Type-A Port 2 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ -- cgit v1.2.3