From d4a12ec82204b9acf8dc814103e4f2efefecd248 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Fri, 11 Jan 2019 11:54:09 -0800 Subject: mb/google/sarien: Enable Camarillo Device Whiskeylake processor have an internal device called Camarillo dedicated for thermal management support, turn it on so processor thermal driver can be loaded. BUG=N/A TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0 can be seen. Signed-off-by: Lijian Zhao Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7 Reviewed-on: https://review.coreboot.org/c/30858 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 + src/mainboard/google/sarien/variants/sarien/devicetree.cb | 1 + 2 files changed, 2 insertions(+) (limited to 'src/mainboard/google/sarien/variants') diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index fa926aea09..ff26cbf49f 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -35,6 +35,7 @@ chip soc/intel/cannonlake register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" + register "Device4Enable" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 48404a8b64..37ef3dc5e0 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -44,6 +44,7 @@ chip soc/intel/cannonlake register "SlowSlewRateForFivr" = "2" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" + register "Device4Enable" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port -- cgit v1.2.3