From c6b041a12e56f32be37b809357225e762b070117 Mon Sep 17 00:00:00 2001 From: "Jes B. Klinke" Date: Tue, 19 Apr 2022 14:00:33 -0700 Subject: tpm: Refactor TPM Kconfig dimensions Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Tim Wawrzynczak Reviewed-by: Julius Werner --- src/mainboard/google/sarien/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/sarien/Kconfig') diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 32a253e13a..37c72ad663 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -10,10 +10,10 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select I2C_TPM select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_EC_REGION select SAR_ENABLE @@ -22,6 +22,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE select SOC_INTEL_WHISKEYLAKE select SPD_READ_BY_WORD + select TPM_GOOGLE_CR50 select USE_SAR config BOARD_GOOGLE_ARCADA -- cgit v1.2.3