From be19c54585e4515811068370fa17ce8f4ea2a2bb Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 22 Aug 2014 13:36:12 -0700 Subject: samus: Updates for EVT board - Remove NFC GPIOs - Change EC wake to GPIO27 - Enable wake on HOTWORD_DET_L_3V3 - Add new Hynix memory SKU BUG=chrome-os-partner:31549 BRANCH=none TEST=emerge-samus coreboot, cannot fully test until EVT Original-Change-Id: Ia25fc39f0b67c53305b3fd9150117d6a7867eb3a Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/213796 Original-Reviewed-by: Aaron Durbin (cherry picked from commit 740ac0bb7eaa9ae35fce8a04825f9c5ecf7cab79) Signed-off-by: Marc Jones Change-Id: I2b1c194eae2ebc53291f078c00ba04f82e10b0c1 Reviewed-on: http://review.coreboot.org/8963 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/samus/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/samus/devicetree.cb') diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index 95ab44be1e..4bbc3af84b 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -45,6 +45,9 @@ chip soc/intel/broadwell register "sata_port_map" = "0x1" register "sio_acpi_mode" = "1" + # Set I2C0 to 1.8V + register "sio_i2c0_voltage" = "1" + # Force enable ASPM for PCIe Port 3 register "pcie_port_force_aspm" = "0x04" register "pcie_port_coalesce" = "1" -- cgit v1.2.3