From ddc3e42c2267fe175dcc28e38f53f0adecf1aa4e Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 2 Oct 2013 16:10:54 -0700 Subject: samus: Add coreboot board Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Stefan Reinauer --- src/mainboard/google/samus/chromeos.c | 102 ++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 src/mainboard/google/samus/chromeos.c (limited to 'src/mainboard/google/samus/chromeos.c') diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c new file mode 100644 index 0000000000..092833c5c5 --- /dev/null +++ b/src/mainboard/google/samus/chromeos.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +#if CONFIG_EC_GOOGLE_CHROMEEC +#include "ec.h" +#include +#endif + +/* SPI Write protect is GPIO 16 */ +#define CROS_WP_GPIO 16 + +#ifndef __PRE_RAM__ +#include + +#define GPIO_COUNT 6 + +static int get_lid_switch(void) +{ +#if CONFIG_EC_GOOGLE_CHROMEEC + u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); + + return !!(ec_switches & EC_SWITCH_LID_OPEN); +#else + return 0; +#endif +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, CROS_WP_GPIO, ACTIVE_HIGH, "write protect", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", + get_recovery_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", + get_lid_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); +} +#endif + +/* The dev-switch is virtual */ +int get_developer_mode_switch(void) +{ + return 0; +} + +/* There are actually two recovery switches. One is the magic keyboard chord, + * the other is driven by Servo. */ +int get_recovery_mode_switch(void) +{ +#if CONFIG_EC_GOOGLE_CHROMEEC + u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); + u32 ec_events; + + /* If a switch is set, we don't need to look at events. */ + if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) + return 1; + + /* Else check if the EC has posted the keyboard recovery event. */ + ec_events = google_chromeec_get_events_b(); + + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +#else + return 0; +#endif +} + +int get_write_protect_state(void) +{ + return get_gpio(CROS_WP_GPIO); +} -- cgit v1.2.3