From 36fd82dfc4523adc08cce5d553b8ae8575e77ab5 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 20 Nov 2014 17:02:17 -0800 Subject: nyan/rush/veyron: Align ChromeOS GPIOs to new model This CL makes slight changes to the ChromeOS-specific GPIO definitions of Tegra and Rockchip boards to prepare them for new features in depthcharge. It adds descriptions for the EC in RW and reset GPIOs, changes the value Tegra writes into the (previously unused) 'port' field to describe the complete GPIO information, and removes code to sample some GPIOs that don't need to be sampled at coreboot time (to help depthcharge detect errors and avoid using a stale value for something that should always represent the current state). BRANCH=None BUG=None TEST=None (tested together with depthcharge patches) Change-Id: I3774979dbe7cacce4932c85810596d80e5664028 Signed-off-by: Stefan Reinauer Original-Commit-Id: df295d0432fbf623597cf36ebb170bd4f63ee08d Original-Change-Id: I36bb16c8d931f862bf12a5b862b10cf18d738ddd Original-Signed-off-by: Julius Werner Original-Reviewed-on: https://chromium-review.googlesource.com/231222 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/9570 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/google/rush_ryu/chromeos.c | 22 +++++++++++++++++++--- src/mainboard/google/rush_ryu/gpio.h | 4 ++-- 2 files changed, 21 insertions(+), 5 deletions(-) (limited to 'src/mainboard/google/rush_ryu') diff --git a/src/mainboard/google/rush_ryu/chromeos.c b/src/mainboard/google/rush_ryu/chromeos.c index 2fd9bb1048..6781b39954 100644 --- a/src/mainboard/google/rush_ryu/chromeos.c +++ b/src/mainboard/google/rush_ryu/chromeos.c @@ -40,7 +40,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) int count = 0; /* Write Protect: active low */ - gpios->gpios[count].port = WRITE_PROTECT_L_INDEX; + gpios->gpios[count].port = WRITE_PROTECT_L; gpios->gpios[count].polarity = ACTIVE_LOW; gpios->gpios[count].value = gpio_get(WRITE_PROTECT_L); strncpy((char *)gpios->gpios[count].name, "write protect", @@ -58,9 +58,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* TODO(adurbin): add lid switch */ /* Power: active low / high depending on board id */ - gpios->gpios[count].port = POWER_BUTTON_INDEX; + gpios->gpios[count].port = POWER_BUTTON; gpios->gpios[count].polarity = get_pwr_btn_polarity(); - gpios->gpios[count].value = gpio_get(POWER_BUTTON); + gpios->gpios[count].value = -1; strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); count++; @@ -73,6 +73,22 @@ void fill_lb_gpios(struct lb_gpios *gpios) GPIO_MAX_NAME_LENGTH); count++; + /* EC in RW: active high */ + gpios->gpios[count].port = EC_IN_RW; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "EC in RW", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Reset: active low (output) */ + gpios->gpios[count].port = AP_SYS_RESET_L; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "reset", + GPIO_MAX_NAME_LENGTH); + count++; + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); gpios->count = count; diff --git a/src/mainboard/google/rush_ryu/gpio.h b/src/mainboard/google/rush_ryu/gpio.h index a813d42332..8fa7c3d07d 100644 --- a/src/mainboard/google/rush_ryu/gpio.h +++ b/src/mainboard/google/rush_ryu/gpio.h @@ -57,11 +57,11 @@ enum { /* Write Protect */ SPI_1V8_WP_L = GPIO(R1), WRITE_PROTECT_L = SPI_1V8_WP_L, - WRITE_PROTECT_L_INDEX = GPIO_R1_INDEX, /* Power button - Depending on board id, maybe active high / low */ BTN_AP_PWR = GPIO(Q0), POWER_BUTTON = BTN_AP_PWR, - POWER_BUTTON_INDEX = GPIO_Q0_INDEX, + /* EC in RW signal */ + EC_IN_RW = GPIO(U4), /* Panel related GPIOs */ LCD_EN = GPIO(H5), -- cgit v1.2.3