From 5be9959e73b7b9e46786b17d264e00a3fc9e7def Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 8 Aug 2022 17:33:37 +0000 Subject: mb/google/rex: Describe TCSS USB ports in devicetree This patch describes the TCSS USB ports in devicetree to generate ACPI code at runtime. The ACPI code includes the port definition, location, type information. BUG=b:224325352 TEST=Able to build and boot MTLRVP. Signed-off-by: Subrata Banik Change-Id: I08613b31aad47cbf573ed1b5fc68c91cf973e190 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66540 Reviewed-by: Ivy Jian Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal --- .../google/rex/variants/rex0/overridetree.cb | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/rex') diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 3231f46568..5732f7b180 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -107,7 +107,26 @@ chip soc/intel/meteorlake device ref tbt_pcie_rp1 on end device ref tbt_pcie_rp2 on end device ref tbt_pcie_rp3 on end - device ref tcss_xhci on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end device ref tcss_dma0 on end device ref tcss_dma1 on end device ref cnvi_wifi on -- cgit v1.2.3