From 4866712b04a4fc6f1a72cd668de0ac91fc9a2a74 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 16 Mar 2024 18:11:53 +0530 Subject: soc/intel/mtl: Enable RAMTOP caching at SoC level for MTL devices This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration at the SoC level for all MTL devices. This change streamlines the configuration process, avoiding redundant selections on individual mainboards. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot functionality on google/ovis and google/rex. Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/rex/Kconfig | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mainboard/google/rex') diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index b1626511a8..880680a2ae 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -43,7 +43,6 @@ config BOARD_GOOGLE_BASEBOARD_OVIS select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE - select SOC_INTEL_COMMON_BASECODE_RAMTOP select SOC_INTEL_IOE_DIE_SUPPORT select SOC_INTEL_METEORLAKE_U_H select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES @@ -59,7 +58,6 @@ config BOARD_GOOGLE_BASEBOARD_REX select HAVE_SLP_S0_GATE select MAINBOARD_HAS_CHROMEOS select MEMORY_SOLDERDOWN - select SOC_INTEL_COMMON_BASECODE_RAMTOP select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_IOE_DIE_SUPPORT select SOC_INTEL_METEORLAKE_U_H -- cgit v1.2.3