From 1a7d2038684415b7698822512aa4553a8b1d3bf7 Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Thu, 1 Jun 2023 12:09:00 +0000 Subject: mb/google/rex/variants/ovis: Add I2C config BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Signed-off-by: Jakub Czapiga Change-Id: I1644b1d8f49accbb2ea68e236534df80a5151360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75503 Reviewed-by: Jan Dabros Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal --- .../google/rex/variants/ovis/overridetree.cb | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'src/mainboard/google/rex') diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index b68840fad0..2d43a0e122 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -1,4 +1,39 @@ chip soc/intel/meteorlake + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C4 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + device domain 0 on + device ref i2c4 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)" + device i2c 50 on end + end + end end end -- cgit v1.2.3