From c15281f91d30db47cbeeaa6077823d604f9cc10e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 8 Aug 2022 18:14:54 +0000 Subject: mb/google/rex: Add OC pin programming for USB2 Port 8 This patch adds OC pin programming for USB2 Port 8. BUG=b:224325352 TEST=Able to build and boot MTLRVP. Signed-off-by: Subrata Banik Change-Id: Ic9dcaef5972d6c0e9fe264445ea10fcd9a82619f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66543 Reviewed-by: Ivy Jian Reviewed-by: Tarun Tuli Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/mainboard/google/rex/variants/rex0/overridetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/rex/variants/rex0') diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index c38721d363..3231f46568 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -4,6 +4,7 @@ chip soc/intel/meteorlake register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # DCI register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth -- cgit v1.2.3