From bcefbe163f70ef2590be252057d626e788047b16 Mon Sep 17 00:00:00 2001
From: Tim Chen <Tim-Chen@quantatw.com>
Date: Fri, 25 Aug 2017 11:00:14 +0800
Subject: mainboard/google/coral: Add USB2 phy setting override for Santa

In order to pass type C USB2 eye diagram for sku Santa,
USB2 port#1 PHY register needs to be overridden.

port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2

BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage

Change-Id: I07c0b7b0f08263a348befb7d6fd8d01028314470
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 .../google/reef/variants/coral/mainboard.c         | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'src/mainboard/google/reef/variants')

diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c
index 3da54569bc..c60c083eac 100644
--- a/src/mainboard/google/reef/variants/coral/mainboard.c
+++ b/src/mainboard/google/reef/variants/coral/mainboard.c
@@ -16,6 +16,13 @@
 #include <stdint.h>
 #include <ec/google/chromeec/ec.h>
 #include "baseboard/variants.h"
+#include <soc/cpu.h>
+#include <soc/intel/apollolake/chip.h>
+
+enum {
+	SKU_2_SANTA = 2,
+	SKU_3_SANTA = 3
+};
 
 uint8_t variant_board_sku(void)
 {
@@ -31,3 +38,22 @@ void variant_nhlt_oem_overrides(const char **oem_id,
 	*oem_table_id = CONFIG_VARIANT_DIR;
 	*oem_revision = variant_board_sku();
 }
+
+void mainboard_devtree_update(struct device *dev)
+{
+       /* Override dev tree settings per board */
+	struct soc_intel_apollolake_config *cfg = dev->chip_info;
+	uint8_t sku_id;
+
+	sku_id = variant_board_sku();
+
+	switch (sku_id) {
+	case SKU_2_SANTA:
+	case SKU_3_SANTA:
+		cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7;
+		cfg->usb2eye[1].Usb20PerPortTxiSet = 2;
+		break;
+	default:
+		break;
+	}
+}
-- 
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