From 2adb50d32e8cd9c61773b1d60de545255c6a4049 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Sat, 9 May 2020 15:37:09 +0530 Subject: apollolake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Apollo Lake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on octopus system Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/reef/variants/coral/devicetree.cb | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google/reef/variants/coral') diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 00e63bc94c..f987e1da02 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -52,12 +52,14 @@ chip soc/intel/apollolake # Enable DPTF register "dptf_enable" = "1" - # PL1 override 12000 mW: the energy calculation is wrong with the + # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "power_limits_config" = "{ + .tdp_pl1_override = 12, + .tdp_pl2_override = 15, + }" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" -- cgit v1.2.3